Design of high speed PCB

When new designers think of the word “high speed,” they are likely to default to clock speed. However, the high-speed design has nothing to do with the clock rate, but with the edge rate or the rate at which the signal level swings between digital states. There is no clear boundary between high-speed PCB and low-speed PCB, so the high-speed PCB design criteria should be kept in mind when designing new designs with advanced components.

High speed routing criteria

In addition to the above design points of impedance control, wiring should be carefully carried out. Here are some important guidelines for any high speed PCB layout:

Minimize the use of vias. If the design of vias is not correct, the impedance will be discontinuous, resulting in reflection and attenuation. Ideally, the total number of vias on the interconnect should be limited to no more than 2.

Use length equalization if necessary. For differential pairs, each end of a pair must have the same length within a certain tolerance. This is important to ensure that the receiver can eliminate common mode noise on the interconnect. For a single ended signal, it may be necessary to route multiple signals in parallel (for example, on a bus) so that the signals arrive at the destination at the same time.

It is better to use a shorter routing length. The signal will lose energy with the passage of time, resulting in dielectric absorption. This means that you should choose to use shorter routing to minimize attenuation. Many signaling standards, such as LVDS and USB, specify the maximum allowable PCB routing length.

Pay attention to the line spacing. The signal should not be placed too close to reduce the intensity of crosstalk. Note that you can never eliminate crosstalk, but you can reduce it by placing appropriate space between adjacent signals. Don’t believe the old “3W” rule here. Instead, the crosstalk simulation is run in a simple layout to determine the correct routing spacing.

Wiring high speed PCB to ensure signal integrity

The signal integrity in PCB design is to ensure the required impedance and minimize the loss. The loss in the substrate and the loss due to the roughness of copper will affect the behavior of the signal. When selecting the sequence of signal, power supply and ground plane, you need to select the appropriate material in the PCB stack.

Another important aspect of high speed PCB wiring and signal integrity is correct component placement and layout. Your CAD tools need to help you route carefully to meet your design constraints. When your PCB design software is completely rule driven, it is easy to route signals through the correct termination scheme or impedance control, thus minimizing crosstalk and suppressing signal reflection.

Power integrity of high speed PCB

A common problem in poorly designed digital boards is that the power consumption of processor components is reduced when they are running at high clock rates. When there are multiple gate switches in the digital module, they will absorb a large amount of current, and the fast current from the regulator will produce a strong transient ripple on the PDN. This ripple may cause the power to be removed from the selected component, causing a component such as MCU or FPGA to shut down or reset. The problem that the digital processor can’t run at full speed / clock rate is not only the problem of capacitor decoupling, but also the problem of stack design.

In high speed PCB design, the main power integrity problem you need to face is the transient ringing on PDN. It’s a digital problem and an analog problem, although it’s hard to solve in the digital field. For digital signal, the bandwidth is much wider than that of analog signal, and the signal can span multiple resonances in PDN impedance spectrum. The goal of PDN design is to select the decoupling capacitor wisely and place it on the key components in order to adjust the shape and peak height of PDN impedance spectrum.

The use of decoupling capacitor is the gospel touted by most designers, sometimes called the only way to solve the power integrity problem of digital system. However, once we look at the PDN impedance spectrum, we find that providing a higher interplane capacitance is the best way to keep the PDN impedance low and smooth the PDN impedance peak. Note that this should be done in addition to using decoupling capacitors and bypass capacitors. In high-speed PCB, keeping the PDN impedance at a low level will keep the transient ripple on the PDN low. This in turn reduces the phase noise (i.e., jitter) of the signal output from the component. Although you can never completely eliminate the transient response on the PDN, you can reduce the intensity of the transient response to a position where it will not cause power drop and component failure.